x86/ucode: Drop the sanity check for interrupts being disabled

Of the substantial number of things which can go wrong during microcode load,
this is not one.  Loading occurs entirely within the boundary of a single
WRMSR instruction.  Its certainly not a BUG()-worthy condition.

Xen has legitimate reasons to not want interrupts enabled at this point, but
that is to do with organising the system rendezvous.  As these are private low
level helpers invoked only from the microcode core logic, forgo the check
entirely.

While dropping system.h, clean up the processor.h include which was an
oversight in the previous header cleanup.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/amd.c
index 96b80ff960124b00d6b810ee830197a2db653b21..9efc03c810816efaedc7ed9af547024c4450bb6d 100644 (file)
--- a/xen/arch/x86/cpu/microcode/amd.c
+++ b/xen/arch/x86/cpu/microcode/amd.c
@@ -20,8 +20,6 @@
 
 #include <asm/hvm/svm/svm.h>
 #include <asm/msr.h>
-#include <asm/processor.h>
-#include <asm/system.h>
 
 #include "private.h"
 
@@ -232,8 +230,6 @@ static int apply_microcode(const struct microcode_patch *patch)
 
     hdr = patch->mc_amd->mpb;
 
-    BUG_ON(local_irq_is_enabled());
-
     hw_err = wrmsr_safe(MSR_AMD_PATCHLOADER, (unsigned long)hdr);
 
     /* get patch id after patching */

diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcode/intel.c
index 78455aa0aeae79e6f9dddac9be895bd35f4977db..49c46cd146d2871f22a3cdfd9e5b4dfaeaa41ec6 100644 (file)
--- a/xen/arch/x86/cpu/microcode/intel.c
+++ b/xen/arch/x86/cpu/microcode/intel.c
@@ -25,8 +25,6 @@
 #include <xen/init.h>
 
 #include <asm/msr.h>
-#include <asm/processor.h>
-#include <asm/system.h>
 
 #include "private.h"
 
@@ -283,8 +281,6 @@ static int apply_microcode(const struct microcode_patch *patch)
 
     mc_intel = patch->mc_intel;
 
-    BUG_ON(local_irq_is_enabled());
-
     /* write microcode via MSR 0x79 */
     wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc_intel->bits);
     wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL);